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Comparing the UltraSPARC T2 Plus to Other Recent SPARC Processors

Update - now the UltraSPARC T2 Plus has been released, and is
available in several new several Sun servers. Allan Packer has
published a new collection
of blog entries
that provide lots of detail.

Here is my updated table of details comparing a number of current
SPARC processors. I can not guarantee 100% accuracy on this, but I
did quite a bit of reading...





























































































































































































NameUltraSPARC IV+®SPARC64TM VIUltraSPARCTM T1UltraSPARCTM T2UltraSPARCTM T2 Plus
CodenamePantherOlympus-CNiagaraNiagara 2Victoria Falls
Physical
process90nm90nm90nm65nm65nm
die size335 mm2421 mm2379 mm2342 mm2
pins136819331831
transistors295 M540 M279 M503 M
clock1.5 – 2.1 GHz2.15 – 2.4 GHz1.0 – 1.4 GHz1.0 – 1.4 GHz1.2 – 1.4 GHz
Architecture
cores22888
threads/core12488
threads/chip24326464
FPU : IU1 : 11 : 11 : 81 : 11 : 1
integration8 × small crypto8 × large crypto, PCI-E, 2 × 10Gbe8 × large crypto, PCI-E, multi-socket
coherency
virtualizationdomains1hypervisor
L1 i$64K/core128K/core16K/core
L1 d$64K/core128K/core8K/core
L2 cache (on-chip)2MB, shared, 4-way, 64B lines6MB, shared, 10-way, 256B lines3MB, shared, 12-way, 64B lines4MB, shared, 16-way, 64B lines
L3 cache 32MB shared, 4-way, tags on-chip, 64B lines n/a n/a
MMUon-chip
on-chip, 4 × DDR2on-chip, 4 × FB-DIMMon-chip, 2 × FB-DIMM
Memory ModelsTSOTSOTSO, limited RMO
Physical Address Space43 bits47 bits40 bits
i-TLB16 FA + 512 2-way SA64 FA
d-TLB16 FA + 512 2-way SA64 FA128 FA
combined TLB32 FA + 2048 2-way SA
Page sizes8K, 64K, 512K, 4M, 32M, 256M8K, 64K, 512K, 4M, 32M, 256M8K, 64K, 4M, 256M
Memory bandwidth2 (GB/sec) 9.6 25.6 60+ 32

Footnotes


  • 1 - domains are implemented above the processor/chip level

  • 2 - theoretical peak - does not take cache coherency or other limits into account

Glossary

  • FA - fully-associative
  • FPU - Floating Point Unit
  • i-TLB - Instruction Translation Lookaside Buffer (d means Data)
  • IU - Integer (execution) Unit
  • L1 - Level 1 (similarly for L2, L3)
  • MMU - Memory Management Unit
  • RMO - Relaxed Memory Order
  • SA - set-associative
  • TSO - Total Store Order

References:

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Comments ( 1 )
  • Lamparelli Monday, May 5, 2008

    What about ROCK? It would be nice to see it listed along with the other high performance processors Sun has developed.


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