Why on-chip accelerators?

In comparison to using onchip crypto accelerators, the use of offchip, look-aside, accelerators, will tend to increase CPU utilization, consume additional I/O bandwidth and introduce additional latency. This tends to make the use of offchip cards problematic for the effective acceleration of bulk ciphers, especially for small or moderately sized packets. While recent announcements for `high-performance' offchip accelerators, using HT or FSB connectivity, may help reduce some of these issues, repeatedly ping-ponging the data off and on chip is inevitably less efficient that using on-chip accelerators that are tightly coupled with the processor cores.


Finally, while in-line (bump-in-the-wire) offchip accelerators can overcome some of these issues, there are other associated issues with this approach – a subject for another day.

Hopefully, I will have actual #s to illustrate these differences in more detail shortly.

[N.B. FIPS140-2 requirements etc. may also dictate choices]

Comments:

I whole-heartedly agree with your points. Have you taken a look at VIA's Padlock on-die crypto unit for their C7 processor? It's accessible as unprivileged instructions, so, for user-space apps, they don't even have to mode-switch into the kernel to access the crypto units. It's amazing how fast they run when you remove the overhead (both mode switching and PCI overhead).

Posted by Derek Morr on October 04, 2007 at 05:42 AM PDT #

There are advantages to discrete on-chip HW accelerators, especially for processors with high thread counts; one can improve utilization and decrease implementation costs my sharing an accelerator between multiple threads. Additionally, by having the accelerator separate from the pipeline, the core is free to continue processing other operations in the background, introducing an additional level of parallelism. However, I would concur that one has to carefully manage the software overheads introduced via a discrete approach versus the essentially zero-overhead in-pipeline accelerator used by VIA.

Posted by Lawrence Spracklen on October 11, 2007 at 04:39 AM PDT #

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About

Dr. Spracklen is a senior staff engineer in the Architecture Technology Group (Sun Microelectronics), that is focused on architecting and modeling next-generation SPARC processors. His current focus is hardware accelerators.

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