Why on-chip accelerators?
By sprack on Oct 04, 2007
In comparison to using onchip crypto accelerators, the use of offchip, look-aside, accelerators, will tend to increase CPU utilization, consume additional I/O bandwidth and introduce additional latency. This tends to make the use of offchip cards problematic for the effective acceleration of bulk ciphers, especially for small or moderately sized packets. While recent announcements for `high-performance' offchip accelerators, using HT or FSB connectivity, may help reduce some of these issues, repeatedly ping-ponging the data off and on chip is inevitably less efficient that using on-chip accelerators that are tightly coupled with the processor cores.
Finally, while in-line (bump-in-the-wire) offchip accelerators can overcome some of these issues, there are other associated issues with this approach – a subject for another day.
Hopefully, I will have actual #s to illustrate these differences in more detail shortly.
[N.B. FIPS140-2 requirements etc. may also dictate choices]