T2 HW crypto and SPECweb2005

I typically witter on about crypto performance at the microbenchmark level, but I was recently browsing the SPECweb05 results and I was impressed to see how the T2 performs, especially on the Banking workload, which is 100% HTTPS:


Processor

SPECweb2005_Banking

1 x T2 [1.4GHz]

70,000

2 x Quad-core Opteron Processor (2356) [2.3GHz]

50,856

2 x Quad-core Xeon Processor X5460 [3.2GHz]

51,840

4 x Quad-core Xeon Processor X7350 [3.0GHz]

71,104


Intel 2-chip http://www.spec.org/web2005/results/res2008q1/web2005-20080225-00104.txt
Intel 4-chip http://www.spec.org/web2005/results/res2007q4/web2005-20071203-00101.html

Opteron http://www.spec.org/web2005/results/res2008q2/web2005-20080409-00107.txt
T2 http://www.spec.org/web2005/results/res2008q2/web2005-20080408-00105.txt


Pretty Impressive! So a single-socket UltraSPARC T2 processor provides equivalent performance to 4-socket x64 systems containing Quad-core processors! On a per socket basis, T2 outperforms the competition by over 2.7X!


Now, this performance leadership is not all down to the HW crypto support – I'm sure the onchip NICs, and abundance of threads help somewhat too. However, the cryptographic overheads associated with HTTPS are pretty significant – RSA ops for session establishment and then RC4 and MD5 (these are the algorithms used for SPECweb2005 anyway) operations to secure and authenticate the subsequent traffic. In fact, looking at the following figures:



Figure 1: Relative costs in an HTTPS transaction for different file sizes. Referenced from here






Figure 2: Typical breakdown of overheads for SPECweb2005 banking





it is apparent that a significant proportion of the total application-level overheads are associated with cryptographic processing. Its therefore not surprising that providing HW support to accelerate cryptographic processing provides a significant performance advantage to the UltraSPARC T2 processor on SPECweb05 banking...


Its nice to see that the good microbenchmark numbers actually translate into significant gains at an application level....

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Dr. Spracklen is a senior staff engineer in the Architecture Technology Group (Sun Microelectronics), that is focused on architecting and modeling next-generation SPARC processors. His current focus is hardware accelerators.

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