T2 Crypto -- accelerator details

The first UltraSPARC processor with on-chip cryptographic accelerators was the UltraSPARC T1 processor; each of the processor's eight cores has an associated crypto accelerator that is targeted at offloading/accelerating public-key cryptography. Basically, this accelerator, termed the modular arithmetic unit (MAU), performs modular exponentiation operations that lie at the heart of algorithms such as RSA and Diffie-Hellman.

With the UltraSPARC T2 processor, each core's crypto accelerator retains its MAU unit, but is also enhanced by the introduction of a cipher/hash unit, that is focussed on accelerating symmetric ciphers (AES etc) and secure hashes (SHA etc).

On the T2, the two sub-units that constitute the accelerator can operate in parallel, such that each core's accelerator can be performing an RSA operation and an AES operation in parallel.

Communication with the cipher/hash unit is via a memory-based control word queue. To offload an operation to the accelerator, it is necessary to generate a control-word that provides the accelerator with the information required to perform the operation e.g. pointers to src, dst, keys, IVs. As a result, the accelerator is essentially stateless, which is extremely important in application spaces where there can be literally thousands of simultaneous connections (e.g. Secure Web, Secure VoIP). Additionally, given this light-weight interface, the overheads associated with offloading an operation to the accelerator can be extremely minimal, allowing even short duration operations to be cost effectively offloaded.

It is possible to interact with the accelerator in a synchronous or asynchronous manner, such that, if desired, it possible to go off and perform other useful processing on the core while the crypto operation is being performed in parallel on the accelerator; this provides an additional level of parallelism that is not achieved when ISA customization is used to achieve crypto acceleration.

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About

Dr. Spracklen is a senior staff engineer in the Architecture Technology Group (Sun Microelectronics), that is focused on architecting and modeling next-generation SPARC processors. His current focus is hardware accelerators.

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