CoolThreads and HPC
By Josh Simons on Dec 06, 2005
Today Sun is announcing its new CoolThreads servers--a huge technology innovation that we believe will change the rules in the datacenter. You will undoubtedly see press and announcements that trumpet the higher levels of achieved application performance, at significantly lower power than competing servers, in significantly less space, and at a lower price point than competitive machines.
But what does this mean for High Performance Computing? Should you run out and buy a rack full of CoolThreads servers to run your next LINPACK or maybe a car crash simulation?
Hell no. Please don't. These servers use the UltraSPARC T1 processor, which has been carefully designed to be highly efficient in serving throughput workloads centered around web infrastructure--running workloads like web and application servers, for example. The T1 has very little floating point capability (one floating point unit to serve all 32 hardware threads.) This isn't a bug---this was precisely the design point we targeted with this first radical CMT (chip multi-threading) processor. We set the dial here on purpose. So don't go running a Monte Carlo simulation on one of these babies--- that's not what it's for.
Will these CoolThreads systems be useful for HPC customers? Sure, in the sense that HPC installations have infrastructure requirements like any other IT-intensive business. You've got web tiers and grid middleware and other non-FP workloads that may benefit significantly from a CoolThreads approach. Plus you have some of the biggest, fullest datacenters on the planet and could probably use some lower power, denser systems. Just keep thinking web infrastructure and integer workloads and you'll be okay.
Does this mean that CMT as a concept is irrelevant to the computing part of HPC? Again, hell no. Don't confuse the UltraSPARC T1, a CMT implementation, with the CMT concept itself. You'll see us set the knobs in a different place with our ROCK CMT processor, for example. We haven't talked much about this chip in public yet, but you'll see a very different (and more interesting) computational profile from that CMT implementation. Stay tuned.
[ T: NiagaraCMT ]