Paper accepted at IWMSE'09, entitled "Transparent Multi-core Cryptographic Support on Niagara CMT Processors."
By user9159837 on Feb 19, 2009
Paper accepted at IWMSE'09, entitled Transparent Multi-core Cryptographic Support on Niagara CMT Processors (pdf).
James Hughes, Gary Morton, Jan Pechanec, Lawrence Spracklen, Bhargava Yenduri, and I co-authored a paper that explores how the Solaris Cryptographic Framework takes transparently advantage of our Niagara multi-core CPU processor line. The paper was accepted for publication and presentation at the Second International Workshop on Multicore Software Engineering (IWMSE09) on May 18, 2009, co-located with the 31st International Conference on Software Engineering (ICSE), May 16-24, 2009 in Vancouver, Canada.
Citation (bibtex entry):
James Hughes, Gary Morton, Jan Pechanec, Christoph Schuba,
Lawrence Spracklen, Bhargava Yenduri. Transparent Multi-core
Cryptographic Support on Niagara CMT Processors. In Proceedings
of the Second International Workshop on Multicore Software
Engineering (IWMSE09). Vancouver, Canada, May 2009.
How cryptographic functionality has been implemented and made available in application scenarios has evolved over time. Pure software implementations were the obvious first choice, followed by dedicated hardware devices, be it co-processors or hardware accelerators accessible on the main bus.
This paper examines aspects of making the next step in this evolution work, namely the use of dedicated cryptographic hardware that's part of multi-core system CPUs. While the inclusion of cryptographic accelerator functionality in the processor chip is not new, this paper investigates the question of how to transparently combine such multi-core cryptographic processor support with higher level software stacks in a commodity operating system that also needs to perform well if such hardware support is not present.
We explore this question in the context of the UltraSPARC T1 and T2 processor family, Chip Multi-Threaded (CMT) processors that have hardware cryptographic accelerators integrated on-chip with 8-core support for symmetric and asymmetric cryptographic and secure hash operations. The paper presents how a software infrastructure, the Solaris Cryptographic Framework, transparently takes advantage of these chip features and presents a brief comparative study of their performance.