Interesting Niagara-2 article

Here is a very interesting article by Rick Merritt at Embedded.com on the Niagara-2 processor which was discussed recently at the Hot Chips symposium. I couldn't make the trip to Hot Chips this year, so I've been perusing the various chip-related media for the good info on what is coming in future hot chips. It is always illuminating.

The most interesting part of the design is the plethora of SERDES (Serializer/Deserializer) interfaces on the chip. These are used to connect to main memory (FBDIMMs), 10 gigabit Ethernet, and PCI-Express interfaces. The cool thing about this is that they are so similar. In previous systems designs you would have a variety of interfaces: parallel memory interfaces (eg. DDR, DDR2), parallel general purpose I/O busses (eg. PCI, PCI-X), serial interfaces (eg. RS-232, Ethernet, Fibre Channel), and a few others (eg. I2C). This meant that the microprocessor design had to implement an assortment of different physical interfaces to the system. By moving to more general purpose SERDES designs, everything becomes simpler. And simple is good.

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