By hendel on May 27, 2006
A quick Intermezzo before I get to "The Unbearable Lightness of Being Stateless". A kind of update to bring other names, places, and faces to my narrative. The magic of number three, a name, a place, and a face.
I have been rambling about how CMT applies horizontal scaling within a chip, and how it eliminates memory sprawl in servers and network elements, well, one of the emerging platforms for such server and network element deployments is ATCA, and it is only natural to put UltraSPARC T1 in an ATCA blade. So we did. The internal code name is Montoya. Now we can do horizontal scaling within the processor, and extend it to the ATCA packet switched interconnect at the shelf or even rack level. 32 threads per Montoya, that means 384 threads per shelf. Some of the ATCA products are already announced and shipping. Montoya was kind of previewed around April at the CTIA show in Vegas, but what happens in Vegas stays in Vegas, so I cannot post a Montoya picture yet.
Well, I will go out on a limb and show you a Montoya picture:
This is Montoya the place. Picture taken last December. Montoya is a small surfer town on the Atlantic South. Waves, cool winds, deserted most of the year but packed with people in January, reachable by car through a single and busy undulating bridge. In engineering lingo Montoya the place is high throughput, bursty, and I/O saturated. A great place for your next vacation. [Note to boss, take the Montoya team to Montoya the place for the Montoya the blade RR/GA celebration.]
Now A face. You were expecting a Montoya face. Wrong. The face is Ashley.
Thought Ashley or Ariel were female names? Wrong again. This is Ashley's pantomimical explanation of a stateless domain moving from "here" to "there", where "here" is around Ashley's solar plexus and "there" is around his right shoulder. So what? Anything worth moving is always moved from here to there or viceversa, but the beauty of Ashley's stateless domains is that they can be moved at all. Ashley's picture was taken in Santa Clara at the Multicore Expo in March, when part of the OpenSPARC community came physically together for the first time to talk about these multicore processor trends. Multicore Expo had the familiar charm of old and small Interops. One could clearly see two distinct themes, low power multicores applied to embedded devices where some of the cores are specialized, and server centric multicore architectures (with Sun's UltraSPARC T1 being the first such incarnation), where the cores are identical although the usage models may be asymmetrical...
Rather than a tired racconto of the Multicore Expo material, here is a link for the CMT presentations, including Ashley's preview of things to come around CMT virtualization. There are other sessions I really enjoyed, but I won't taint you with my opinions, just read them and let's compare notes through my comments section. My session was sandwiched between Teja presenting how to use their tools for FPGA based packet processing, and Intel showing how you can use a dual core Xeon for packet processing. Good stuff, but if you ask me you don't have to use FPGAs anymore for fast packet processing, and you probably don't want to use Xeons for fast packet processing. Why? As I said, ask me. Today is just an Intermezzo about a name, a place, and a face.
And here is an update, a link for Montoya the blade: