Friday Aug 17, 2007

OpenSPARC T1 Version 1.5 Released

This release makes it much easier for people to have an OpenSPARC T1 core on within a system. It's very cool stuff.

Within this release for the first time, there is support for an OpenSPARC T1 FPGA system with UART and DRAM controllers. It also supports the entire Xilinx tool chain for building new FPGA systems using OpenSPARC T1.

On this platform, you can map single thread T1, add right peripherals and then boot Hypervisor. You can also run standalone C program without the OS. Complete documentation and an entire new verification environment are also included as part of this release.

These new features are designed to enable a user to build real systems using the OpenSPARC T1 core. For further details on Xilinx, please refer to the Xilinx University program and information on the ml410 board.

Watch the video demonstration below and Download it!


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OpenSPARC T2 Beta Program

Its been a while since I posted. A lot is happening and its keeping us all very busy on the OpenSPARC Team. If you haven't already heard, UltraSPARC T2 was announced on August 7th, I thought the launch event are very well done and you can watch it here.

We intend to open source the UltraSPARC T2 as OpenSPARC T2. An OpenSPARC T2 beta review was announced. This program provides early access to a limited number of hardware designers and tool developers to begin working with the state-of-the-art CMT processor with server on a chip functionality. The program catalyzes the development of a community for OpenSPARC T2, speeds the debugging process and leads to a better first release of the technology.

Sign-up for the OpenSPARC T2 Beta Program. Please be as completed as possible in your submission, there has been a lot of interested already and we are going to select just a small group from the total number of candidates.

Visit the OpenSPARC.net website. Let me know if you like the new look and feel.

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