Niagara-2: A Highly Threaded Server-on-a-Chip

Greg Grohoski, a Sun Distinguished Engineer and one of the principal architects on the Niagara 2 project, made a presentation on Niagara 2 at the Hot Chips 18 conference on August 20 thru 22, 2006 at the Memorial Auditorium, Stanford University. Greg presented some of the first details of the upcoming Chip Multi-Threading (CMT) design. Highlights of Niagara 2:
  • Niagara-2 combines all major server functions on one chip
  • >2x throughput and throughput/watt vs. UltraSparc T1
  • Greatly improved floating-point performance
  • Significantly improved integer performance
  • Embedded wire-speed cryptographic acceleration
  • Enables new generation of power-efficient, fully-secure datacenters
The presentation: "Niagara 2 A highly Threaded Server On a Chip"

There are also a few articles written:
[ T: ]
<script type="text/javascript" language="javascript"> var sc_project=1115798; var sc_invisible=1; var sc_partition=10; var sc_security="a3cd786a"; </script> <script type="text/javascript" language="javascript" src="http://www.statcounter.com/counter/counter.js"></script>
Comments:

Post a Comment:
Comments are closed for this entry.
About

dwayne

Search

Top Tags
Archives
« April 2014
SunMonTueWedThuFriSat
  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
   
       
Today
Bookmarks