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An Oracle blog about Transactional locks

X86 platform memory model - clarifications in recent Intel manuals

Dave Dice
Senior Research Scientist

Intel has taken steps toward addressing some of the concerns about potential platform memory model relaxations that I identified in a
previous blog entry. Specifically see section 7.2.3.7 of their
latest Software Developer's Manual which now guarantees global store ordering.

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Comments ( 1 )
  • Bartosz Milewski Friday, June 3, 2011
    You mean section 8.2.3.7.
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