By Darryl Gove on Apr 18, 2007
The TLB is a structure on the chip that handles the mapping of virtual memory addresses (used by the application) into physical memory addresses (used by the hardware). It is a list of such mappings, each mapping describes a range of memory (called the page size), the default on SPARC in 8KB page sizes, but it can be configured up to impressively large sizes (eg 256MB for UltraSPARC T1). The command to display what page sizes the hardware supports is pagesize:
If the application requests a virtual to physical translation that is not mapped in the TLB, then there's a TLB miss. On UltraSPARC III/IV the process of fetching a TLB entry takes about a hundred cycles.
Using a larger page size will reduce the number of TLB misses. Of course a large page size requires a large chunk of contiguous physical memory, and it's not always possible to get this.
An application can request large pages in one of three ways:
- Using the ppgsz command to set the preferred page sizes.
- Using the compiler flag -xpagesize= to set the preferred page size at compile time.
- Preloading the mpss.so.1 library and using the MPSSHEAP, MPSSSTACK environment variables to describe the page size.
When an application is running it is possible to inspect the page sizes of the allocated memory using the command:
pmap -xs <pid>