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    August 31, 2012

SPARC Architecture 2011

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With what appears to be minimal fanfare, an update of the SPARC Architecture has been released. If you ever look at SPARC disassembly code, then this is the document that you need to bookmark. If you are not familiar with it, then it basically describes how a SPARC processor should behave - it doesn't describe a particular implementation, just the "generic" processor. As with all revisions, it supercedes the SPARC v9 book published back in the 90s, having both corrections, and definitions of new instructions. Anyway, should be an interesting read :)

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Comments ( 2 )
  • bank kus Friday, August 31, 2012

    Thanks. Few questions:

    * What are Fast Trap Handlers, how many cycles are these typically handled in? Any examples of what they're used for today?

    * Do SPARCs have a fault-on-branch instruction of some sort?

    * Non Cacheable *with-no* side effect. It appears they are un-cached and incoherent, is that correct? Any idea what these are used for? Thread Local memory?

  • Darryl Gove Friday, August 31, 2012

    Fast traps are things like TLB handlers or spill fill traps. Cost is probably around 100 cycles.

    No fault on branch that I'm aware of.

    I have no idea what a non-cacheable with no side-effect operation would be used for. I can't see it being useful in application code, I struggle to see it being useful even for a driver.

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